The present invention relates to technologies which are suitable for a data processor comprised of a memory control unit and a central processing unit, a data processing system comprised of a data processor and a memory, a semiconductor device which has the data processor or data processing system integrated on a single chip, and a semiconductor device which has the data processor or data processing system encapsulated in a single semiconductor package.
In recent years, mobile terminals such as a portable telephone are rapidly equipped with increasingly more functions, including music replay, gaming, communications of moving image data, and so on. It is anticipated that an increase in the amount of data resulting from additional functions of the device will require a significantly larger capacity for a memory embedded in an information processing unit (system LSI) including a microprocessor, or for a memory for external storage. Therefore, in order to implement more additional functions in mobile terminals such as a portable telephone, an increased capacity is essential to the memory embedded in the system LSI and the memory for external storage.
Static random access memories (hereinafter abbreviated as “SRAM”) are typically employed in system LSIs for implementing a microprocessor (MPU) which is tailored to provide functions for commercializing mobile terminals and the like. This is because SRAM is characterized by a particularly high compatibility with logic circuits such as MPU, which facilitates the manufacturing, and by a small current required for holding data therein.
A memory for use with a mobile terminal for external storage is known, for example, from “Combination Memories” searched on the Internet on Apr. 28, 2003, <URL: http://sharp-world.com/products/device/flash/cmlist.html> which describes a composite memory comprised of SRAM and flash memory mounted in a single package. In such a composite memory, the flash memory stores programs for communications and applications, other than an operating system (OS) for a portable telephone system. The SRAM in turn includes areas for storing telephone numbers, addresses, and ringer tones, and a work area which is reserved for temporary use in execution of an application. The SRAM is likewise used in the composite memory because of its requirement of a small current for holding data therein. The composite memory, which has a plurality of memories laminated one on another, also contributes to a reduction in cost resulting from a smaller mounting area.
Before making the present invention, the inventors considered possible problems which would arise when a larger capacity of memory (i.e., SRAM) was provided for higher performance.
First, a larger capacity of SRAM-based memory would cause an increase in the chip size of LSI and a resulting increase in cost. This is because SRAM, which is comprised of six MOS transistors, has a large memory cell area. Also, a larger capacity of SRAM-based memory would cause an increase in a current required for holding data therein. This is because, in addition to an increase in the current for holding data in the additional capacity of the memory, a so-called gate leak current increases due to the use of thinner oxide insulating films required for miniaturization of MOS transistors, thereby causing a consequent increase in the current for holding data.
A solution for the foregoing problem is to use a memory cell which has a smaller memory cell area than SRAM. For example, a SESO (Single Electron Shut Off) memory is described in Bryan Atwood et al., “SESO memory: A CMOS compatible with high density embedded memory technology for mobile application,” 2002 Symposium on VLSI Circuit Digest of Technical Papers, pp. 154-155, (2000). The SESO memory has a smaller memory cell area than SRAM and is therefore integrated at a higher density than SRAM, so that the use of the SESO memory can prevent an increase in the chip size to reduce the cost. In addition, the SESO memory cell exhibits an extremely small leak current, and can therefore reduce a current required for holding data therein. Of course, it should be understood that non-volatile memory cells may be utilized instead. For example, the foregoing first problem can be solved, including an increase in the chip size and the current required for holding data, by use of a non-volatile phase change memory OUM (Ovonic Unified Memory) as disclosed, for example, in Stefan Lai et al., “OUM—A 180 nm nonvolatile memory cell element technology for stand alone and embedded applications,” 2001 IEEE International Electron Devices Meeting Digest of Technical Papers, pp. 803-806, (2001).
However, the foregoing SESO memory and phase change memory have a disadvantageous characteristic of a slow write operation as compared with a read operation. Thus, the inventors noted that the following second problem could arise when such memory cells were utilized to design a large capacity of memory.
When a data processing system is implemented by a central processing unit and a memory, a sequence of write operations can be successively performed in the memory. In this event, a slow write operation would cause a delay in a subsequent memory access for writing, possibly resulting in a significant degradation in system performance.
U.S. Pat. No. 5,530,828 and JP-A-7-93215 describe exemplary solutions for the problem of a memory which presents a slower write operation than a read operation. A semiconductor storage device described in U.S. Pat. No. 5,530,828 has a plurality of flash memories, so that when write operations must be performed in succession, the write operations are not concentrated on the same flash memory, but subsequent write operations are distributed to different flash memories, thereby accomplishing an apparently faster write operation. However, when a write operation is inevitably performed in the same flash memory, a subsequent write access is delayed, so that an address controller must manage an address generated by the processor and a flash memories in which data is written at the address, but such control is extremely difficult. U.S. Pat. No. 5,530,828 does not even disclose any specific solution for the management. JP-A-7-93215 in turn describes a semiconductor storage device which comprises a write buffer and a plurality of dynamic random access memories (hereinafter abbreviated as “DRAM”), wherein an external write operation is performed on the write buffer. However, JP-A-7-93215 does not take into consideration the fact that an increase in write speed is limited by the capacity of the write buffer, and that an amount of data larger than the capacity of the write buffer would cause a subsequent write operation to delay.